Discussion:
[PATCH] Additional X-Gene 1 performance events
(too old to reply)
William Cohen
2016-04-27 15:59:31 UTC
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Raw Message
The initial OProfile X-Gene 1 support only had the ARMv8 generic
performance events. There are many additional microarchitecture
performance events listed for X-Gene 1 at:

https://github.com/AppliedMicro/ENGLinuxLatest/blob/apm_linux_v3.17-rc4/Documentation/arm64/xgene_pmu.txt

This patch adds those X-Gene 1 specific events.

Signed-off-by: William Cohen <***@redhat.com>
---
events/arm/armv8-xgene/events | 78 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)

diff --git a/events/arm/armv8-xgene/events b/events/arm/armv8-xgene/events
index 3e28463..3542978 100644
--- a/events/arm/armv8-xgene/events
+++ b/events/arm/armv8-xgene/events
@@ -5,3 +5,81 @@
# Basic ARM V8 events
#
include:arm/armv8-pmuv3-common
+event:0x040 um:zero minimum:10007 name:L1D_CACHE_LD : L1 data cache access - Read
+event:0x041 um:zero minimum:10007 name:L1D_CACHE_ST : L1 data cache access - Write
+event:0x042 um:zero minimum:10007 name:L1D_CACHE_REFILL_LD : L1 data cache refill - Read
+event:0x048 um:zero minimum:10007 name:L1D_CACHE_INVAL : L1 data cache invalidate
+event:0x04C um:zero minimum:10007 name:L1D_TLB_REFILL_LD : L1 data TLB refill - Read
+event:0x04D um:zero minimum:10007 name:L1D_TLB_REFILL_ST : L1 data TLB refill - Write
+event:0x050 um:zero minimum:10007 name:L2D_CACHE_LD : L2 data cache access - Read
+event:0x051 um:zero minimum:10007 name:L2D_CACHE_ST : L2 data cache access - Write
+event:0x052 um:zero minimum:10007 name:L2D_CACHE_REFILL_LD : L2 data cache refill - Read
+event:0x053 um:zero minimum:10007 name:L2D_CACHE_REFILL_ST : L2 data cache refill - Write
+event:0x056 um:zero minimum:10007 name:L2D_CACHE_WB_VICTIM : L2 data cache write-back - victim
+event:0x057 um:zero minimum:10007 name:L2D_CACHE_WB_CLEAN : L2 data cache write-back - Cleaning and coherency
+event:0x058 um:zero minimum:10007 name:L2D_CACHE_INVAL : L2 data cache invalidate
+event:0x060 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read
+event:0x061 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write
+event:0x062 um:zero minimum:10007 name:BUS_ACCESS_SHARED : Bus access - Normal, cacheable, sharable
+event:0x063 um:zero minimum:10007 name:BUS_ACCESS_NOT_SHARED : Bus access - Not normal, cacheable, sharable
+event:0x064 um:zero minimum:10007 name:BUS_ACCESS_NORMAL : Bus access - Normal
+event:0x065 um:zero minimum:10007 name:BUS_ACCESS_PERIPH : Bus access - Peripheral
+event:0x066 um:zero minimum:10007 name:MEM_ACCESS_LD : Data memory access - Read
+event:0x067 um:zero minimum:10007 name:MEM_ACCESS_ST : Data memory access - write
+event:0x068 um:zero minimum:10007 name:UNALIGNED_LD_SPEC : Unaligned access - Read
+event:0x069 um:zero minimum:10007 name:UNALIGNED_ST_SPEC : Unaligned access - Write
+event:0x06A um:zero minimum:10007 name:UNALIGNED_LDST_SPEC : Unaligned access
+event:0x06C um:zero minimum:10007 name:LDREX_SPEC : Exclusive operation speculatively executed - Load exclusive
+event:0x06D um:zero minimum:10007 name:STREX_PASS_SPEC : Exclusive operation speculative executed - Store exclusive pass
+event:0x06E um:zero minimum:10007 name:STREX_FAIL_SPEC : Exclusive operation speculative executed - Store exclusive fail
+event:0x06F um:zero minimum:10007 name:STREX_SPEC : Exclusive operation speculatively executed - Store exclusive
+event:0x070 um:zero minimum:10007 name:LD_SPEC : Operation speculatively executed - Load
+event:0x071 um:zero minimum:10007 name:ST_SPEC : Operation speculatively executed - Store
+event:0x072 um:zero minimum:10007 name:LDST_SPEC : Operation speculatively executed - Load or store
+event:0x073 um:zero minimum:10007 name:DP_SPEC : Operation speculatively executed - Integer data processing
+event:0x074 um:zero minimum:10007 name:ASE_SPEC : Operation speculatively executed - Advanced SIMD
+event:0x075 um:zero minimum:10007 name:VFP_SPEC : Operation speculatively executed - FP
+event:0x076 um:zero minimum:10007 name:PC_WRITE_SPEC : Operation speculatively executed - Software change of PC
+event:0x078 um:zero minimum:10007 name:BR_IMMED_SPEC : Branch speculative executed - Immediate branch
+event:0x079 um:zero minimum:10007 name:BR_RETURN_SPEC : Branch speculative executed - Procedure return
+event:0x07A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculative executed - Indirect branch
+event:0x07C um:zero minimum:10007 name:ISB_SPEC : Barrier speculatively executed - ISB
+event:0x07D um:zero minimum:10007 name:DSB_SPEC : Barrier speculatively executed - DSB
+event:0x07E um:zero minimum:10007 name:DMB_SPEC : Barrier speculatively executed - DMB
+event:0x081 um:zero minimum:10007 name:EXC_UNDEF : Exception taken, other synchronous
+event:0x082 um:zero minimum:10007 name:EXC_SVC : Exception taken, Supervisor Call
+event:0x083 um:zero minimum:10007 name:EXC_PABORT : Exception taken, Instruction Abort
+event:0x084 um:zero minimum:10007 name:EXC_DABORT : Exception taken, Data Abort or SError
+event:0x086 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ
+event:0x087 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ
+event:0x08A um:zero minimum:10007 name:EXC_HVC : Exception taken, Hypervisor Call
+event:0x08B um:zero minimum:10007 name:EXC_TRAP_PABORT : Exception taken, Instruction Abort not taken locally
+event:0x08C um:zero minimum:10007 name:EXC_TRAP_DABORT : Exception taken, Data Abort or SError not taken locally
+event:0x08D um:zero minimum:10007 name:EXC_TRAP_OTHER : Exception taken, other traps not taken locally
+event:0x08E um:zero minimum:10007 name:EXC_TRAP_IRQ : Exception taken, IRQ not taken locally
+event:0x08F um:zero minimum:10007 name:EXC_TRAP_FIQ : Exception taken, FIQ not taken locally
+event:0x090 um:zero minimum:10007 name:RC_LD_SPEC : Release consistency instruction speculatively executed - Load Acquire
+event:0x091 um:zero minimum:10007 name:RC_ST_SPEC : Release consistency instruction speculatively executed - Store Release
+event:0x100 um:zero minimum:10007 name:NOP_SPEC : Operation speculatively executed - NOP
+event:0x101 um:zero minimum:10007 name:FSU_CLOCK_OFF_CYCLES : FSU clocking gated off cycle
+event:0x102 um:zero minimum:10007 name:BTB_MIS_PRED : BTB misprediction
+event:0x103 um:zero minimum:10007 name:ITB_MISS : ITB miss
+event:0x104 um:zero minimum:10007 name:DTB_MISS : DTB miss
+event:0x105 um:zero minimum:10007 name:L1D_CACHE_LATE_MISS : L1 data cache late miss
+event:0x106 um:zero minimum:10007 name:L1D_CACHE_PREFETCH : L1 data cache prefetch request
+event:0x107 um:zero minimum:10007 name:L2D_CACHE_PREFETCH : L2 data prefetch request
+event:0x108 um:zero minimum:10007 name:DECODE_STALL : Decode starved for instruction cycle
+event:0x109 um:zero minimum:10007 name:DISPATCH_STALL : Op dispatch stalled cycle
+event:0x10A um:zero minimum:10007 name:IXA_STALL : IXA Op non-issue
+event:0x10B um:zero minimum:10007 name:IXB_STALL : IXB Op non-issue
+event:0x10C um:zero minimum:10007 name:BX_STALL : BX Op non-issue
+event:0x10D um:zero minimum:10007 name:LX_STALL : LX Op non-issue
+event:0x10E um:zero minimum:10007 name:SX_STALL : SX Op non-issue
+event:0x10F um:zero minimum:10007 name:FX_STALL : FX Op non-issue
+event:0x110 um:zero minimum:10007 name:WAIT_CYCLES : Wait state cycle
+event:0x111 um:zero minimum:10007 name:L1_STAGE2_TLB_REFILL : L1 stage-2 TLB refill
+event:0x112 um:zero minimum:10007 name:PAGE_WALK_L0_STAGE1_HIT : Page Walk Cache level-0 stage-1 hit
+event:0x113 um:zero minimum:10007 name:PAGE_WALK_L1_STAGE1_HIT : Page Walk Cache level-1 stage-1 hit
+event:0x114 um:zero minimum:10007 name:PAGE_WALK_L2_STAGE1_HIT : Page Walk Cache level-2 stage-1 hit
+event:0x115 um:zero minimum:10007 name:PAGE_WALK_L1_STAGE2_HIT : Page Walk Cache level-1 stage-2 hit
+event:0x116 um:zero minimum:10007 name:PAGE_WALK_L2_STAGE2_HIT : Page Walk Cache level-2 stage-2 hit
--
2.5.5
Michael Petlan
2016-05-03 13:51:21 UTC
Permalink
Raw Message
Post by William Cohen
The initial OProfile X-Gene 1 support only had the ARMv8 generic
performance events. There are many additional microarchitecture
https://github.com/AppliedMicro/ENGLinuxLatest/blob/apm_linux_v3.17-rc4/Documentation/arm64/xgene_pmu.txt
This patch adds those X-Gene 1 specific events.
Hi William,

I sanity-tested these events on an X-Gene box and it looks well.
Anyway, the arm/armv8-pmuv3-common events are still included there,
wouldn't it make sense to remove that and add only those that are
supported on X-Gene just directly to arm/armv8-xgene/events?

I basically mean not to include L1D_CACHE_WB and BUS_CYCLES and
possibly some more of them that should not be there... Ideas?

Michael
Post by William Cohen
---
events/arm/armv8-xgene/events | 78 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/events/arm/armv8-xgene/events b/events/arm/armv8-xgene/events
index 3e28463..3542978 100644
--- a/events/arm/armv8-xgene/events
+++ b/events/arm/armv8-xgene/events
@@ -5,3 +5,81 @@
# Basic ARM V8 events
#
include:arm/armv8-pmuv3-common
+event:0x040 um:zero minimum:10007 name:L1D_CACHE_LD : L1 data cache access - Read
+event:0x041 um:zero minimum:10007 name:L1D_CACHE_ST : L1 data cache access - Write
+event:0x042 um:zero minimum:10007 name:L1D_CACHE_REFILL_LD : L1 data cache refill - Read
+event:0x048 um:zero minimum:10007 name:L1D_CACHE_INVAL : L1 data cache invalidate
+event:0x04C um:zero minimum:10007 name:L1D_TLB_REFILL_LD : L1 data TLB refill - Read
+event:0x04D um:zero minimum:10007 name:L1D_TLB_REFILL_ST : L1 data TLB refill - Write
+event:0x050 um:zero minimum:10007 name:L2D_CACHE_LD : L2 data cache access - Read
+event:0x051 um:zero minimum:10007 name:L2D_CACHE_ST : L2 data cache access - Write
+event:0x052 um:zero minimum:10007 name:L2D_CACHE_REFILL_LD : L2 data cache refill - Read
+event:0x053 um:zero minimum:10007 name:L2D_CACHE_REFILL_ST : L2 data cache refill - Write
+event:0x056 um:zero minimum:10007 name:L2D_CACHE_WB_VICTIM : L2 data cache write-back - victim
+event:0x057 um:zero minimum:10007 name:L2D_CACHE_WB_CLEAN : L2 data cache write-back - Cleaning and coherency
+event:0x058 um:zero minimum:10007 name:L2D_CACHE_INVAL : L2 data cache invalidate
+event:0x060 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read
+event:0x061 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write
+event:0x062 um:zero minimum:10007 name:BUS_ACCESS_SHARED : Bus access - Normal, cacheable, sharable
+event:0x063 um:zero minimum:10007 name:BUS_ACCESS_NOT_SHARED : Bus access - Not normal, cacheable, sharable
+event:0x064 um:zero minimum:10007 name:BUS_ACCESS_NORMAL : Bus access - Normal
+event:0x065 um:zero minimum:10007 name:BUS_ACCESS_PERIPH : Bus access - Peripheral
+event:0x066 um:zero minimum:10007 name:MEM_ACCESS_LD : Data memory access - Read
+event:0x067 um:zero minimum:10007 name:MEM_ACCESS_ST : Data memory access - write
+event:0x068 um:zero minimum:10007 name:UNALIGNED_LD_SPEC : Unaligned access - Read
+event:0x069 um:zero minimum:10007 name:UNALIGNED_ST_SPEC : Unaligned access - Write
+event:0x06A um:zero minimum:10007 name:UNALIGNED_LDST_SPEC : Unaligned access
+event:0x06C um:zero minimum:10007 name:LDREX_SPEC : Exclusive operation speculatively executed - Load exclusive
+event:0x06D um:zero minimum:10007 name:STREX_PASS_SPEC : Exclusive operation speculative executed - Store exclusive pass
+event:0x06E um:zero minimum:10007 name:STREX_FAIL_SPEC : Exclusive operation speculative executed - Store exclusive fail
+event:0x06F um:zero minimum:10007 name:STREX_SPEC : Exclusive operation speculatively executed - Store exclusive
+event:0x070 um:zero minimum:10007 name:LD_SPEC : Operation speculatively executed - Load
+event:0x071 um:zero minimum:10007 name:ST_SPEC : Operation speculatively executed - Store
+event:0x072 um:zero minimum:10007 name:LDST_SPEC : Operation speculatively executed - Load or store
+event:0x073 um:zero minimum:10007 name:DP_SPEC : Operation speculatively executed - Integer data processing
+event:0x074 um:zero minimum:10007 name:ASE_SPEC : Operation speculatively executed - Advanced SIMD
+event:0x075 um:zero minimum:10007 name:VFP_SPEC : Operation speculatively executed - FP
+event:0x076 um:zero minimum:10007 name:PC_WRITE_SPEC : Operation speculatively executed - Software change of PC
+event:0x078 um:zero minimum:10007 name:BR_IMMED_SPEC : Branch speculative executed - Immediate branch
+event:0x079 um:zero minimum:10007 name:BR_RETURN_SPEC : Branch speculative executed - Procedure return
+event:0x07A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculative executed - Indirect branch
+event:0x07C um:zero minimum:10007 name:ISB_SPEC : Barrier speculatively executed - ISB
+event:0x07D um:zero minimum:10007 name:DSB_SPEC : Barrier speculatively executed - DSB
+event:0x07E um:zero minimum:10007 name:DMB_SPEC : Barrier speculatively executed - DMB
+event:0x081 um:zero minimum:10007 name:EXC_UNDEF : Exception taken, other synchronous
+event:0x082 um:zero minimum:10007 name:EXC_SVC : Exception taken, Supervisor Call
+event:0x083 um:zero minimum:10007 name:EXC_PABORT : Exception taken, Instruction Abort
+event:0x084 um:zero minimum:10007 name:EXC_DABORT : Exception taken, Data Abort or SError
+event:0x086 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ
+event:0x087 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ
+event:0x08A um:zero minimum:10007 name:EXC_HVC : Exception taken, Hypervisor Call
+event:0x08B um:zero minimum:10007 name:EXC_TRAP_PABORT : Exception taken, Instruction Abort not taken locally
+event:0x08C um:zero minimum:10007 name:EXC_TRAP_DABORT : Exception taken, Data Abort or SError not taken locally
+event:0x08D um:zero minimum:10007 name:EXC_TRAP_OTHER : Exception taken, other traps not taken locally
+event:0x08E um:zero minimum:10007 name:EXC_TRAP_IRQ : Exception taken, IRQ not taken locally
+event:0x08F um:zero minimum:10007 name:EXC_TRAP_FIQ : Exception taken, FIQ not taken locally
+event:0x090 um:zero minimum:10007 name:RC_LD_SPEC : Release consistency instruction speculatively executed - Load Acquire
+event:0x091 um:zero minimum:10007 name:RC_ST_SPEC : Release consistency instruction speculatively executed - Store Release
+event:0x100 um:zero minimum:10007 name:NOP_SPEC : Operation speculatively executed - NOP
+event:0x101 um:zero minimum:10007 name:FSU_CLOCK_OFF_CYCLES : FSU clocking gated off cycle
+event:0x102 um:zero minimum:10007 name:BTB_MIS_PRED : BTB misprediction
+event:0x103 um:zero minimum:10007 name:ITB_MISS : ITB miss
+event:0x104 um:zero minimum:10007 name:DTB_MISS : DTB miss
+event:0x105 um:zero minimum:10007 name:L1D_CACHE_LATE_MISS : L1 data cache late miss
+event:0x106 um:zero minimum:10007 name:L1D_CACHE_PREFETCH : L1 data cache prefetch request
+event:0x107 um:zero minimum:10007 name:L2D_CACHE_PREFETCH : L2 data prefetch request
+event:0x108 um:zero minimum:10007 name:DECODE_STALL : Decode starved for instruction cycle
+event:0x109 um:zero minimum:10007 name:DISPATCH_STALL : Op dispatch stalled cycle
+event:0x10A um:zero minimum:10007 name:IXA_STALL : IXA Op non-issue
+event:0x10B um:zero minimum:10007 name:IXB_STALL : IXB Op non-issue
+event:0x10C um:zero minimum:10007 name:BX_STALL : BX Op non-issue
+event:0x10D um:zero minimum:10007 name:LX_STALL : LX Op non-issue
+event:0x10E um:zero minimum:10007 name:SX_STALL : SX Op non-issue
+event:0x10F um:zero minimum:10007 name:FX_STALL : FX Op non-issue
+event:0x110 um:zero minimum:10007 name:WAIT_CYCLES : Wait state cycle
+event:0x111 um:zero minimum:10007 name:L1_STAGE2_TLB_REFILL : L1 stage-2 TLB refill
+event:0x112 um:zero minimum:10007 name:PAGE_WALK_L0_STAGE1_HIT : Page Walk Cache level-0 stage-1 hit
+event:0x113 um:zero minimum:10007 name:PAGE_WALK_L1_STAGE1_HIT : Page Walk Cache level-1 stage-1 hit
+event:0x114 um:zero minimum:10007 name:PAGE_WALK_L2_STAGE1_HIT : Page Walk Cache level-2 stage-1 hit
+event:0x115 um:zero minimum:10007 name:PAGE_WALK_L1_STAGE2_HIT : Page Walk Cache level-1 stage-2 hit
+event:0x116 um:zero minimum:10007 name:PAGE_WALK_L2_STAGE2_HIT : Page Walk Cache level-2 stage-2 hit
--
2.5.5
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William Cohen
2016-05-03 14:10:31 UTC
Permalink
Raw Message
Post by Michael Petlan
Post by William Cohen
The initial OProfile X-Gene 1 support only had the ARMv8 generic
performance events. There are many additional microarchitecture
https://github.com/AppliedMicro/ENGLinuxLatest/blob/apm_linux_v3.17-rc4/Documentation/arm64/xgene_pmu.txt
This patch adds those X-Gene 1 specific events.
Hi William,
I sanity-tested these events on an X-Gene box and it looks well.
Anyway, the arm/armv8-pmuv3-common events are still included there,
wouldn't it make sense to remove that and add only those that are
supported on X-Gene just directly to arm/armv8-xgene/events?
Hi Michael,

Some of the newer event sets for Intel processors such as goldmont that support the architected events have done something similar. So that is an option.
Post by Michael Petlan
I basically mean not to include L1D_CACHE_WB and BUS_CYCLES and
possibly some more of them that should not be there... Ideas?
One other thing that I noticed was that I put a complete set of event for xgene in to libpfm some time ago. I would like revise the oprofile names and make them agree with the libpfm ones. It is annoying to have variations in the event naming between tools

So I need to revise the patch to pull in the only the pmuv3 events that are supported and adjust the event names.

-Will
Post by Michael Petlan
Michael
Post by William Cohen
---
events/arm/armv8-xgene/events | 78 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/events/arm/armv8-xgene/events b/events/arm/armv8-xgene/events
index 3e28463..3542978 100644
--- a/events/arm/armv8-xgene/events
+++ b/events/arm/armv8-xgene/events
@@ -5,3 +5,81 @@
# Basic ARM V8 events
#
include:arm/armv8-pmuv3-common
+event:0x040 um:zero minimum:10007 name:L1D_CACHE_LD : L1 data cache access - Read
+event:0x041 um:zero minimum:10007 name:L1D_CACHE_ST : L1 data cache access - Write
+event:0x042 um:zero minimum:10007 name:L1D_CACHE_REFILL_LD : L1 data cache refill - Read
+event:0x048 um:zero minimum:10007 name:L1D_CACHE_INVAL : L1 data cache invalidate
+event:0x04C um:zero minimum:10007 name:L1D_TLB_REFILL_LD : L1 data TLB refill - Read
+event:0x04D um:zero minimum:10007 name:L1D_TLB_REFILL_ST : L1 data TLB refill - Write
+event:0x050 um:zero minimum:10007 name:L2D_CACHE_LD : L2 data cache access - Read
+event:0x051 um:zero minimum:10007 name:L2D_CACHE_ST : L2 data cache access - Write
+event:0x052 um:zero minimum:10007 name:L2D_CACHE_REFILL_LD : L2 data cache refill - Read
+event:0x053 um:zero minimum:10007 name:L2D_CACHE_REFILL_ST : L2 data cache refill - Write
+event:0x056 um:zero minimum:10007 name:L2D_CACHE_WB_VICTIM : L2 data cache write-back - victim
+event:0x057 um:zero minimum:10007 name:L2D_CACHE_WB_CLEAN : L2 data cache write-back - Cleaning and coherency
+event:0x058 um:zero minimum:10007 name:L2D_CACHE_INVAL : L2 data cache invalidate
+event:0x060 um:zero minimum:10007 name:BUS_ACCESS_LD : Bus access - Read
+event:0x061 um:zero minimum:10007 name:BUS_ACCESS_ST : Bus access - Write
+event:0x062 um:zero minimum:10007 name:BUS_ACCESS_SHARED : Bus access - Normal, cacheable, sharable
+event:0x063 um:zero minimum:10007 name:BUS_ACCESS_NOT_SHARED : Bus access - Not normal, cacheable, sharable
+event:0x064 um:zero minimum:10007 name:BUS_ACCESS_NORMAL : Bus access - Normal
+event:0x065 um:zero minimum:10007 name:BUS_ACCESS_PERIPH : Bus access - Peripheral
+event:0x066 um:zero minimum:10007 name:MEM_ACCESS_LD : Data memory access - Read
+event:0x067 um:zero minimum:10007 name:MEM_ACCESS_ST : Data memory access - write
+event:0x068 um:zero minimum:10007 name:UNALIGNED_LD_SPEC : Unaligned access - Read
+event:0x069 um:zero minimum:10007 name:UNALIGNED_ST_SPEC : Unaligned access - Write
+event:0x06A um:zero minimum:10007 name:UNALIGNED_LDST_SPEC : Unaligned access
+event:0x06C um:zero minimum:10007 name:LDREX_SPEC : Exclusive operation speculatively executed - Load exclusive
+event:0x06D um:zero minimum:10007 name:STREX_PASS_SPEC : Exclusive operation speculative executed - Store exclusive pass
+event:0x06E um:zero minimum:10007 name:STREX_FAIL_SPEC : Exclusive operation speculative executed - Store exclusive fail
+event:0x06F um:zero minimum:10007 name:STREX_SPEC : Exclusive operation speculatively executed - Store exclusive
+event:0x070 um:zero minimum:10007 name:LD_SPEC : Operation speculatively executed - Load
+event:0x071 um:zero minimum:10007 name:ST_SPEC : Operation speculatively executed - Store
+event:0x072 um:zero minimum:10007 name:LDST_SPEC : Operation speculatively executed - Load or store
+event:0x073 um:zero minimum:10007 name:DP_SPEC : Operation speculatively executed - Integer data processing
+event:0x074 um:zero minimum:10007 name:ASE_SPEC : Operation speculatively executed - Advanced SIMD
+event:0x075 um:zero minimum:10007 name:VFP_SPEC : Operation speculatively executed - FP
+event:0x076 um:zero minimum:10007 name:PC_WRITE_SPEC : Operation speculatively executed - Software change of PC
+event:0x078 um:zero minimum:10007 name:BR_IMMED_SPEC : Branch speculative executed - Immediate branch
+event:0x079 um:zero minimum:10007 name:BR_RETURN_SPEC : Branch speculative executed - Procedure return
+event:0x07A um:zero minimum:10007 name:BR_INDIRECT_SPEC : Branch speculative executed - Indirect branch
+event:0x07C um:zero minimum:10007 name:ISB_SPEC : Barrier speculatively executed - ISB
+event:0x07D um:zero minimum:10007 name:DSB_SPEC : Barrier speculatively executed - DSB
+event:0x07E um:zero minimum:10007 name:DMB_SPEC : Barrier speculatively executed - DMB
+event:0x081 um:zero minimum:10007 name:EXC_UNDEF : Exception taken, other synchronous
+event:0x082 um:zero minimum:10007 name:EXC_SVC : Exception taken, Supervisor Call
+event:0x083 um:zero minimum:10007 name:EXC_PABORT : Exception taken, Instruction Abort
+event:0x084 um:zero minimum:10007 name:EXC_DABORT : Exception taken, Data Abort or SError
+event:0x086 um:zero minimum:10007 name:EXC_IRQ : Exception taken, IRQ
+event:0x087 um:zero minimum:10007 name:EXC_FIQ : Exception taken, FIQ
+event:0x08A um:zero minimum:10007 name:EXC_HVC : Exception taken, Hypervisor Call
+event:0x08B um:zero minimum:10007 name:EXC_TRAP_PABORT : Exception taken, Instruction Abort not taken locally
+event:0x08C um:zero minimum:10007 name:EXC_TRAP_DABORT : Exception taken, Data Abort or SError not taken locally
+event:0x08D um:zero minimum:10007 name:EXC_TRAP_OTHER : Exception taken, other traps not taken locally
+event:0x08E um:zero minimum:10007 name:EXC_TRAP_IRQ : Exception taken, IRQ not taken locally
+event:0x08F um:zero minimum:10007 name:EXC_TRAP_FIQ : Exception taken, FIQ not taken locally
+event:0x090 um:zero minimum:10007 name:RC_LD_SPEC : Release consistency instruction speculatively executed - Load Acquire
+event:0x091 um:zero minimum:10007 name:RC_ST_SPEC : Release consistency instruction speculatively executed - Store Release
+event:0x100 um:zero minimum:10007 name:NOP_SPEC : Operation speculatively executed - NOP
+event:0x101 um:zero minimum:10007 name:FSU_CLOCK_OFF_CYCLES : FSU clocking gated off cycle
+event:0x102 um:zero minimum:10007 name:BTB_MIS_PRED : BTB misprediction
+event:0x103 um:zero minimum:10007 name:ITB_MISS : ITB miss
+event:0x104 um:zero minimum:10007 name:DTB_MISS : DTB miss
+event:0x105 um:zero minimum:10007 name:L1D_CACHE_LATE_MISS : L1 data cache late miss
+event:0x106 um:zero minimum:10007 name:L1D_CACHE_PREFETCH : L1 data cache prefetch request
+event:0x107 um:zero minimum:10007 name:L2D_CACHE_PREFETCH : L2 data prefetch request
+event:0x108 um:zero minimum:10007 name:DECODE_STALL : Decode starved for instruction cycle
+event:0x109 um:zero minimum:10007 name:DISPATCH_STALL : Op dispatch stalled cycle
+event:0x10A um:zero minimum:10007 name:IXA_STALL : IXA Op non-issue
+event:0x10B um:zero minimum:10007 name:IXB_STALL : IXB Op non-issue
+event:0x10C um:zero minimum:10007 name:BX_STALL : BX Op non-issue
+event:0x10D um:zero minimum:10007 name:LX_STALL : LX Op non-issue
+event:0x10E um:zero minimum:10007 name:SX_STALL : SX Op non-issue
+event:0x10F um:zero minimum:10007 name:FX_STALL : FX Op non-issue
+event:0x110 um:zero minimum:10007 name:WAIT_CYCLES : Wait state cycle
+event:0x111 um:zero minimum:10007 name:L1_STAGE2_TLB_REFILL : L1 stage-2 TLB refill
+event:0x112 um:zero minimum:10007 name:PAGE_WALK_L0_STAGE1_HIT : Page Walk Cache level-0 stage-1 hit
+event:0x113 um:zero minimum:10007 name:PAGE_WALK_L1_STAGE1_HIT : Page Walk Cache level-1 stage-1 hit
+event:0x114 um:zero minimum:10007 name:PAGE_WALK_L2_STAGE1_HIT : Page Walk Cache level-2 stage-1 hit
+event:0x115 um:zero minimum:10007 name:PAGE_WALK_L1_STAGE2_HIT : Page Walk Cache level-1 stage-2 hit
+event:0x116 um:zero minimum:10007 name:PAGE_WALK_L2_STAGE2_HIT : Page Walk Cache level-2 stage-2 hit
--
2.5.5
------------------------------------------------------------------------------
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